Synchronous or clocked semiconductor integrated circuits have circuits that are driven by a clock signal. Typically, an input clock is provided to the synchronous semiconductor integrated circuits and internal circuits of the integrated circuits are driven by the input clock or a derivative of the input clock.
In clocked controlled integrated circuits, one major concern during operation is with sequencing and capturing of various internal timing signals. Internal timing signals are generated from both synchronous events which are clock-based and timed from the rising or falling edge of the input clock and asynchronous events which are based on gate delays and/or wire interconnect delays due to the resistance and capacitance of the interconnect wires of the integrated circuit, referred to as RC delays. The first group of internal timing signals—those generated from synchronous events and with timing stems mostly from clock gating—have minimal or no temperature, wafer manufacturing process or voltage dependency on their timing. The first group of internal timing signals will however be directly dependent on the clock frequency. The second group of internal timing signals—those generated from asynchronous events and whose timing stems mostly from gate delays and RC delays—will have their timing being shifted or varied over the allowable range of different temperature, manufacturing process and voltage operating conditions.
In certain situations, internal timing signals can enter into a collision domain. Timing collision occurs when the arrival of a data signal does not match up with a capture signal that is intended to trap and store that data signal. In one example, an output buffer in a clocked integrated circuit is implemented as a first-in-first-out (FIFO) register which is clocked by the input clock or a derivative of the input clock. A collision domain event can occur when data from a subsequent memory read operation, a predominantly asynchronous event, over-writes the data that is latched in an output buffer before the latched data has been read out by the receiving system. In another example, such as during high speed operation, RC delays may cause data from a read operation to arrive at the output buffer later than the time requested and therefore the clocked integrated circuit sends out invalid data.